cartTop Project Status (07/29/2016 - 14:46:22) | |||
Project File: | ARVHDL.xise | Parser Errors: | No Errors |
Module Name: | cartTop | Implementation State: | Fitted |
Target Device: | xc9572xl-10VQ64 |
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No Errors |
Product Version: | ISE 14.7 |
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2 Warnings (0 new) |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | So 30. lip 12:15:02 2016 | 0 | 2 Warnings (0 new) | 0 | |
Translation Report | Current | So 30. lip 12:15:08 2016 | 0 | 0 | 0 | |
CPLD Fitter Report (Text) | Current | So 30. lip 12:15:13 2016 | 0 | 1 Warning (1 new) | 1 Info (1 new) | |
Power Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
Post-Fit Simulation Model Report |