cartTop Project Status (07/29/2016 - 14:46:22)
Project File: ARVHDL.xise Parser Errors: No Errors
Module Name: cartTop Implementation State: Fitted
Target Device: xc9572xl-10VQ64
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
2 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSo 30. lip 12:15:02 201602 Warnings (0 new)0
Translation ReportCurrentSo 30. lip 12:15:08 2016000
CPLD Fitter Report (Text)CurrentSo 30. lip 12:15:13 201601 Warning (1 new)1 Info (1 new)
Power Report     
 
Secondary Reports [-]
Report NameStatusGenerated
Post-Fit Simulation Model Report  

Date Generated: 06/24/2018 - 14:29:13