********** Mapped Logic ********** |
BUFEX <= (ROM_LOW AND IO2); |
FDCPE_D0: FDCPE port map (D0_I,D0.PIN,NOT FI2,NOT RESET,'0',D0_CE);
D0_CE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT O_OE AND NOT IO1 AND NOT RW AND NOT A1 AND NOT A0); D0 <= D0_I when D0_OE = '1' else 'Z'; D0_OE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT O_OE AND NOT IO1 AND RW AND NOT A1 AND NOT A0); |
FDCPE_D1: FDCPE port map (D1_I,D1.PIN,NOT FI2,NOT RESET,'0',D1_CE);
D1_CE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT O_OE AND NOT IO1 AND NOT RW AND NOT A1 AND NOT A0); D1 <= D1_I when D1_OE = '1' else 'Z'; D1_OE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT O_OE AND NOT IO1 AND RW AND NOT A1 AND NOT A0); |
FDCPE_D2: FDCPE port map (D2_I,D2.PIN,NOT FI2,NOT RESET,'0',D2_CE);
D2_CE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT O_OE AND NOT IO1 AND NOT RW AND NOT A1 AND NOT A0); D2 <= D2_I when D2_OE = '1' else 'Z'; D2_OE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT O_OE AND NOT IO1 AND RW AND NOT A1 AND NOT A0); |
FDCPE_D3: FDCPE port map (D3_I,D3.PIN,NOT FI2,NOT RESET,'0',D3_CE);
D3_CE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT O_OE AND NOT IO1 AND NOT RW AND NOT A1 AND NOT A0); D3 <= D3_I when D3_OE = '1' else 'Z'; D3_OE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT O_OE AND NOT IO1 AND RW AND NOT A1 AND NOT A0); |
FDCPE_D4: FDCPE port map (D4_I,D4.PIN,NOT FI2,NOT RESET,'0',D4_CE);
D4_CE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT O_OE AND NOT IO1 AND NOT RW AND NOT A1 AND NOT A0); D4 <= D4_I when D4_OE = '1' else 'Z'; D4_OE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT O_OE AND NOT IO1 AND RW AND NOT A1 AND NOT A0); |
FDCPE_D5: FDCPE port map (D5_I,D5.PIN,NOT FI2,NOT RESET,'0',D5_CE);
D5_CE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT O_OE AND NOT IO1 AND NOT RW AND NOT A1 AND NOT A0); D5 <= D5_I when D5_OE = '1' else 'Z'; D5_OE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT O_OE AND NOT IO1 AND RW AND NOT A1 AND NOT A0); |
FDCPE_D6: FDCPE port map (D6_I,D6.PIN,NOT FI2,NOT RESET,'0',D6_CE);
D6_CE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT O_OE AND NOT IO1 AND NOT RW AND NOT A1 AND NOT A0); D6 <= D6_I when D6_OE = '1' else 'Z'; D6_OE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT O_OE AND NOT IO1 AND RW AND NOT A1 AND NOT A0); |
FDCPE_D7: FDCPE port map (D7_I,D7.PIN,NOT FI2,NOT RESET,'0',D7_CE);
D7_CE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT O_OE AND NOT IO1 AND NOT RW AND NOT A1 AND NOT A0); D7 <= D7_I when D7_OE = '1' else 'Z'; D7_OE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT O_OE AND NOT IO1 AND RW AND NOT A1 AND NOT A0); |
FDCPE_EXROM: FDCPE port map (EXROM,D1.PIN,NOT FI2,NOT RESET,'0',EXROM_CE);
EXROM_CE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT O_OE AND NOT IO1 AND NOT RW AND NOT A1 AND NOT A0); |
GAME <= '1'; |
MEM_CS <= '1'; |
MEM_WE <= '1'; |
NMI_OUT <= '1'; |
FDCPE_O_A13: FDCPE port map (O_A13,D3.PIN,NOT FI2,NOT RESET,'0',O_A13_CE);
O_A13_CE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT O_OE AND NOT IO1 AND NOT RW AND NOT A1 AND NOT A0); |
FDCPE_O_A14: FDCPE port map (O_A14,D4.PIN,NOT FI2,NOT RESET,'0',O_A14_CE);
O_A14_CE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT O_OE AND NOT IO1 AND NOT RW AND NOT A1 AND NOT A0); |
FDCPE_O_A15: FDCPE port map (O_A15,D5.PIN,NOT FI2,NOT RESET,'0',O_A15_CE);
O_A15_CE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT O_OE AND NOT IO1 AND NOT RW AND NOT A1 AND NOT A0); |
FDCPE_O_A16: FDCPE port map (O_A16,D6.PIN,NOT FI2,NOT RESET,'0',O_A16_CE);
O_A16_CE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT O_OE AND NOT IO1 AND NOT RW AND NOT A1 AND NOT A0); |
FDCPE_O_A17: FDCPE port map (O_A17,D7.PIN,NOT FI2,NOT RESET,'0',O_A17_CE);
O_A17_CE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT O_OE AND NOT IO1 AND NOT RW AND NOT A1 AND NOT A0); |
FDCPE_O_A18: FDCPE port map (O_A18,D3.PIN,NOT FI2,NOT RESET,'0',O_A18_CE);
O_A18_CE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT O_OE AND NOT IO1 AND NOT RW AND NOT A1 AND NOT A0); |
O_CE <= (ROM_LOW AND IO2); |
FDCPE_O_OE: FDCPE port map (O_OE,D2.PIN,NOT FI2,NOT RESET,'0',O_OE_CE);
O_OE_CE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT O_OE AND NOT IO1 AND NOT RW AND NOT A1 AND NOT A0); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); |