cartTop Project Status (08/05/2016 - 22:15:49)
Project File: ARRAMVHDL.xise Parser Errors: No Errors
Module Name: cartTop Implementation State: Synthesized (Failed)
Target Device: xc9572xl-10VQ64
  • Errors:
X 2 Errors (2 new)
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentPt 5. sie 22:15:47 2016X 2 Errors (2 new)00
Translation ReportOut of DateSo 30. lip 12:21:48 2016000
CPLD Fitter Report (Text)Out of DateSo 30. lip 12:21:52 201602 Warnings (1 new)2 Infos (2 new)
Power Report     
 
Secondary Reports [-]
Report NameStatusGenerated
Post-Fit Simulation Model Report  

Date Generated: 08/05/2016 - 22:16:17