cpldfit: version P.20131013 Xilinx Inc. Fitter Report Design Name: cartTop Date: 7-30-2016, 12:21PM Device Used: XC9572XL-10-VQ64 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 22 /72 ( 31%) 58 /360 ( 16%) 67 /216 ( 31%) 15 /72 ( 21%) 38 /52 ( 73%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 1/18 13/54 4/90 9/13 FB2 8/18 19/54 31/90 10/13 FB3 11/18 22/54 20/90 14/14* FB4 2/18 13/54 3/90 5/12 ----- ----- ----- ----- 22/72 67/216 58/360 38/52 * - Resource is exhausted ** Global Control Resources ** Signal 'FI2' mapped onto global clock net GCK1. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 15 15 | I/O : 33 46 Output : 14 14 | GCK/IO : 2 3 Bidirectional : 8 8 | GTS/IO : 2 2 GCK : 1 1 | GSR/IO : 1 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 38 38 ** Power Data ** There are 22 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'cartTop.ise'. INFO:Cpld - Inferring BUFG constraint for signal 'A15' based upon the LOC constraint 'P17'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. INFO:Cpld - Inferring BUFG constraint for signal 'FI2' based upon the LOC constraint 'P15'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. WARNING:Cpld:1239 - The global clock designation (BUFG) on signal 'A15_IBUF' is ignored. Most likely the signal is gated and therefore cannot be used as a global control signal. ************************* Summary of Mapped Logic ************************ ** 22 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State D7 4 13 FB1_3 12 I/O I/O STD FAST RESET O_A13 3 13 FB2_5 61 I/O O STD FAST RESET D3 4 13 FB2_6 62 I/O I/O STD FAST RESET D4 4 13 FB2_8 63 I/O I/O STD FAST RESET D1 4 13 FB2_9 64 GSR/I/O I/O STD FAST RESET D6 4 13 FB2_10 1 I/O I/O STD FAST RESET D0 4 13 FB2_11 2 GTS/I/O I/O STD FAST RESET D5 4 13 FB2_12 4 I/O I/O STD FAST RESET D2 4 13 FB2_14 5 GTS/I/O I/O STD FAST RESET O_A15 3 13 FB3_2 22 I/O O STD FAST RESET O_A16 3 13 FB3_3 31 I/O O STD FAST RESET O_A17 3 13 FB3_4 32 I/O O STD FAST RESET O_A18 3 13 FB3_6 34 I/O O STD FAST RESET MEM_CS 2 5 FB3_8 25 I/O O STD FAST EXROM 3 13 FB3_9 27 I/O O STD FAST RESET GAME 0 0 FB3_10 39 I/O O STD FAST MEM_WE 1 2 FB3_11 33 I/O O STD FAST O_CE 0 0 FB3_12 40 I/O O STD FAST BUFEX 2 4 FB3_14 35 I/O O STD FAST O_OE 0 0 FB3_17 38 I/O O STD FAST O_A14 3 13 FB4_2 43 I/O O STD FAST RESET NMI_OUT 0 0 FB4_17 57 I/O O STD FAST ** 16 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use RW FB1_2 8 I/O I A14 FB1_4 13 I/O I A13 FB1_8 11 I/O I FI2 FB1_9 15 GCK/I/O GCK/I A7 FB1_12 23 I/O I A15 FB1_14 17 GCK/I/O I A5 FB1_15 19 I/O I A6 FB1_17 20 I/O I IO1 FB2_4 59 I/O I A3 FB2_15 6 I/O I A0 FB3_5 24 I/O I RESET FB3_15 36 I/O I A4 FB3_16 42 I/O I A2 FB4_3 46 I/O I IO2 FB4_8 45 I/O I A1 FB4_14 50 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X - Signal used as input to the macrocell logic. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 13/41 Number of signals used by logic mapping into function block: 13 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB1_1 (b) (unused) 0 0 0 5 FB1_2 8 I/O I D7 4 0 0 1 FB1_3 12 I/O I/O (unused) 0 0 0 5 FB1_4 13 I/O I (unused) 0 0 0 5 FB1_5 9 I/O (unused) 0 0 0 5 FB1_6 10 I/O (unused) 0 0 0 5 FB1_7 (b) (unused) 0 0 0 5 FB1_8 11 I/O I (unused) 0 0 0 5 FB1_9 15 GCK/I/O GCK/I (unused) 0 0 0 5 FB1_10 18 I/O (unused) 0 0 0 5 FB1_11 16 GCK/I/O (unused) 0 0 0 5 FB1_12 23 I/O I (unused) 0 0 0 5 FB1_13 (b) (unused) 0 0 0 5 FB1_14 17 GCK/I/O I (unused) 0 0 0 5 FB1_15 19 I/O I (unused) 0 0 0 5 FB1_16 (b) (unused) 0 0 0 5 FB1_17 20 I/O I (unused) 0 0 0 5 FB1_18 (b) Signals Used by Logic in Function Block 1: A0 6: A5 10: IO1 2: A1 7: A6 11: D7.PIN 3: A2 8: A7 12: RESET 4: A3 9: D2 13: RW 5: A4 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs D7 XXXXXXXXXXXXX........................... 13 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 19/35 Number of signals used by logic mapping into function block: 19 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB2_1 (b) (unused) 0 0 0 5 FB2_2 60 I/O (unused) 0 0 0 5 FB2_3 58 I/O (unused) 0 0 0 5 FB2_4 59 I/O I O_A13 3 0 0 2 FB2_5 61 I/O O D3 4 0 0 1 FB2_6 62 I/O I/O (unused) 0 0 0 5 FB2_7 (b) D4 4 0 0 1 FB2_8 63 I/O I/O D1 4 0 0 1 FB2_9 64 GSR/I/O I/O D6 4 0 0 1 FB2_10 1 I/O I/O D0 4 0 0 1 FB2_11 2 GTS/I/O I/O D5 4 0 0 1 FB2_12 4 I/O I/O (unused) 0 0 0 5 FB2_13 (b) D2 4 0 0 1 FB2_14 5 GTS/I/O I/O (unused) 0 0 0 5 FB2_15 6 I/O I (unused) 0 0 0 5 FB2_16 (b) (unused) 0 0 0 5 FB2_17 7 I/O (unused) 0 0 0 5 FB2_18 (b) Signals Used by Logic in Function Block 1: A0 8: A7 14: D3.PIN 2: A1 9: D2 15: D4.PIN 3: A2 10: IO1 16: D5.PIN 4: A3 11: D0.PIN 17: D6.PIN 5: A4 12: D1.PIN 18: RESET 6: A5 13: D2.PIN 19: RW 7: A6 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs O_A13 XXXXXXXXXX...X...XX..................... 13 D3 XXXXXXXXXX...X...XX..................... 13 D4 XXXXXXXXXX....X..XX..................... 13 D1 XXXXXXXXXX.X.....XX..................... 13 D6 XXXXXXXXXX......XXX..................... 13 D0 XXXXXXXXXXX......XX..................... 13 D5 XXXXXXXXXX.....X.XX..................... 13 D2 XXXXXXXXXX..X....XX..................... 13 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 22/32 Number of signals used by logic mapping into function block: 22 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB3_1 (b) O_A15 3 0 0 2 FB3_2 22 I/O O O_A16 3 0 0 2 FB3_3 31 I/O O O_A17 3 0 0 2 FB3_4 32 I/O O (unused) 0 0 0 5 FB3_5 24 I/O I O_A18 3 0 0 2 FB3_6 34 I/O O (unused) 0 0 0 5 FB3_7 (b) MEM_CS 2 0 0 3 FB3_8 25 I/O O EXROM 3 0 0 2 FB3_9 27 I/O O GAME 0 0 0 5 FB3_10 39 I/O O MEM_WE 1 0 0 4 FB3_11 33 I/O O O_CE 0 0 0 5 FB3_12 40 I/O O (unused) 0 0 0 5 FB3_13 (b) BUFEX 2 0 0 3 FB3_14 35 I/O O (unused) 0 0 0 5 FB3_15 36 I/O I (unused) 0 0 0 5 FB3_16 42 I/O I O_OE 0 0 0 5 FB3_17 38 I/O O (unused) 0 0 0 5 FB3_18 (b) Signals Used by Logic in Function Block 1: A0 9: A5 16: D1.PIN 2: A13 10: A6 17: D3.PIN 3: A14 11: A7 18: D5.PIN 4: A15 12: D2 19: D6.PIN 5: A1 13: FI2 20: D7.PIN 6: A2 14: IO1 21: RESET 7: A3 15: IO2 22: RW 8: A4 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs O_A15 X...XXXXXXXX.X...X..XX.................. 13 O_A16 X...XXXXXXXX.X....X.XX.................. 13 O_A17 X...XXXXXXXX.X.....XXX.................. 13 O_A18 X...XXXXXXXX.X..X...XX.................. 13 MEM_CS .XXX.......X..X......................... 5 EXROM X...XXXXXXXX.X.X....XX.................. 13 GAME ........................................ 0 MEM_WE ............X........X.................. 2 O_CE ........................................ 0 BUFEX .XXX..........X......................... 4 O_OE ........................................ 0 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 13/41 Number of signals used by logic mapping into function block: 13 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB4_1 (b) O_A14 3 0 0 2 FB4_2 43 I/O O (unused) 0 0 0 5 FB4_3 46 I/O I (unused) 0 0 0 5 FB4_4 47 I/O (unused) 0 0 0 5 FB4_5 44 I/O (unused) 0 0 0 5 FB4_6 49 I/O (unused) 0 0 0 5 FB4_7 (b) (unused) 0 0 0 5 FB4_8 45 I/O I (unused) 0 0 0 5 FB4_9 (b) (unused) 0 0 0 5 FB4_10 51 I/O (unused) 0 0 0 5 FB4_11 48 I/O (unused) 0 0 0 5 FB4_12 52 I/O (unused) 0 0 0 5 FB4_13 (b) (unused) 0 0 0 5 FB4_14 50 I/O I (unused) 0 0 0 5 FB4_15 56 I/O (unused) 0 0 0 5 FB4_16 (b) NMI_OUT 0 0 0 5 FB4_17 57 I/O O (unused) 0 0 0 5 FB4_18 (b) Signals Used by Logic in Function Block 1: A0 6: A5 10: IO1 2: A1 7: A6 11: D4.PIN 3: A2 8: A7 12: RESET 4: A3 9: D2 13: RW 5: A4 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs O_A14 XXXXXXXXXXXXX........................... 13 NMI_OUT ........................................ 0 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** BUFEX <= NOT (((NOT IO2) OR (A15 AND NOT A14 AND NOT A13))); FDCPE_D0: FDCPE port map (D0_I,D0.PIN,NOT FI2,NOT RESET,'0',D0_CE); D0_CE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT D2 AND NOT IO1 AND NOT RW AND NOT A1 AND NOT A0); D0 <= D0_I when D0_OE = '1' else 'Z'; D0_OE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT D2 AND NOT IO1 AND RW AND NOT A1 AND NOT A0); FDCPE_D1: FDCPE port map (D1_I,D1.PIN,NOT FI2,NOT RESET,'0',D1_CE); D1_CE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT D2 AND NOT IO1 AND NOT RW AND NOT A1 AND NOT A0); D1 <= D1_I when D1_OE = '1' else 'Z'; D1_OE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT D2 AND NOT IO1 AND RW AND NOT A1 AND NOT A0); FDCPE_D2: FDCPE port map (D2_I,D2.PIN,NOT FI2,NOT RESET,'0',D2_CE); D2_CE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT D2 AND NOT IO1 AND NOT RW AND NOT A1 AND NOT A0); D2 <= D2_I when D2_OE = '1' else 'Z'; D2_OE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT D2 AND NOT IO1 AND RW AND NOT A1 AND NOT A0); FDCPE_D3: FDCPE port map (D3_I,D3.PIN,NOT FI2,NOT RESET,'0',D3_CE); D3_CE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT D2 AND NOT IO1 AND NOT RW AND NOT A1 AND NOT A0); D3 <= D3_I when D3_OE = '1' else 'Z'; D3_OE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT D2 AND NOT IO1 AND RW AND NOT A1 AND NOT A0); FDCPE_D4: FDCPE port map (D4_I,D4.PIN,NOT FI2,NOT RESET,'0',D4_CE); D4_CE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT D2 AND NOT IO1 AND NOT RW AND NOT A1 AND NOT A0); D4 <= D4_I when D4_OE = '1' else 'Z'; D4_OE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT D2 AND NOT IO1 AND RW AND NOT A1 AND NOT A0); FDCPE_D5: FDCPE port map (D5_I,D5.PIN,NOT FI2,NOT RESET,'0',D5_CE); D5_CE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT D2 AND NOT IO1 AND NOT RW AND NOT A1 AND NOT A0); D5 <= D5_I when D5_OE = '1' else 'Z'; D5_OE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT D2 AND NOT IO1 AND RW AND NOT A1 AND NOT A0); FDCPE_D6: FDCPE port map (D6_I,D6.PIN,NOT FI2,NOT RESET,'0',D6_CE); D6_CE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT D2 AND NOT IO1 AND NOT RW AND NOT A1 AND NOT A0); D6 <= D6_I when D6_OE = '1' else 'Z'; D6_OE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT D2 AND NOT IO1 AND RW AND NOT A1 AND NOT A0); FDCPE_D7: FDCPE port map (D7_I,D7.PIN,NOT FI2,NOT RESET,'0',D7_CE); D7_CE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT D2 AND NOT IO1 AND NOT RW AND NOT A1 AND NOT A0); D7 <= D7_I when D7_OE = '1' else 'Z'; D7_OE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT D2 AND NOT IO1 AND RW AND NOT A1 AND NOT A0); FDCPE_EXROM: FDCPE port map (EXROM,D1.PIN,NOT FI2,NOT RESET,'0',EXROM_CE); EXROM_CE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT D2 AND NOT IO1 AND NOT RW AND NOT A1 AND NOT A0); GAME <= '1'; MEM_CS <= NOT (((NOT D2 AND NOT IO2) OR (NOT D2 AND A15 AND NOT A14 AND NOT A13))); MEM_WE <= NOT ((FI2 AND NOT RW)); NMI_OUT <= '1'; FDCPE_O_A13: FDCPE port map (O_A13,D3.PIN,NOT FI2,NOT RESET,'0',O_A13_CE); O_A13_CE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT D2 AND NOT IO1 AND NOT RW AND NOT A1 AND NOT A0); FDCPE_O_A14: FDCPE port map (O_A14,D4.PIN,NOT FI2,NOT RESET,'0',O_A14_CE); O_A14_CE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT D2 AND NOT IO1 AND NOT RW AND NOT A1 AND NOT A0); FDCPE_O_A15: FDCPE port map (O_A15,D5.PIN,NOT FI2,NOT RESET,'0',O_A15_CE); O_A15_CE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT D2 AND NOT IO1 AND NOT RW AND NOT A1 AND NOT A0); FDCPE_O_A16: FDCPE port map (O_A16,D6.PIN,NOT FI2,NOT RESET,'0',O_A16_CE); O_A16_CE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT D2 AND NOT IO1 AND NOT RW AND NOT A1 AND NOT A0); FDCPE_O_A17: FDCPE port map (O_A17,D7.PIN,NOT FI2,NOT RESET,'0',O_A17_CE); O_A17_CE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT D2 AND NOT IO1 AND NOT RW AND NOT A1 AND NOT A0); FDCPE_O_A18: FDCPE port map (O_A18,D3.PIN,NOT FI2,NOT RESET,'0',O_A18_CE); O_A18_CE <= (NOT A7 AND NOT A6 AND NOT A5 AND NOT A4 AND NOT A3 AND NOT A2 AND NOT D2 AND NOT IO1 AND NOT RW AND NOT A1 AND NOT A0); O_CE <= '1'; O_OE <= '1'; Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC9572XL-10-VQ64 ----------------------------------------------- /48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 \ | 49 32 | | 50 31 | | 51 30 | | 52 29 | | 53 28 | | 54 27 | | 55 26 | | 56 XC9572XL-10-VQ64 25 | | 57 24 | | 58 23 | | 59 22 | | 60 21 | | 61 20 | | 62 19 | | 63 18 | | 64 17 | \ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 / ----------------------------------------------- Pin Signal Pin Signal No. Name No. Name 1 D6 33 MEM_WE 2 D0 34 O_A18 3 VCC 35 BUFEX 4 D5 36 RESET 5 D2 37 VCC 6 A3 38 O_OE 7 KPR 39 GAME 8 RW 40 O_CE 9 KPR 41 GND 10 KPR 42 A4 11 A13 43 O_A14 12 D7 44 KPR 13 A14 45 IO2 14 GND 46 A2 15 FI2 47 KPR 16 KPR 48 KPR 17 A15 49 KPR 18 KPR 50 A1 19 A5 51 KPR 20 A6 52 KPR 21 GND 53 TDO 22 O_A15 54 GND 23 A7 55 VCC 24 A0 56 KPR 25 MEM_CS 57 NMI_OUT 26 VCC 58 KPR 27 EXROM 59 IO1 28 TDI 60 KPR 29 TMS 61 O_A13 30 TCK 62 D3 31 O_A16 63 D4 32 O_A17 64 D1 Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal KPR = Unused I/O with weak keeper (leave unconnected) VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc9572xl-10-VQ64 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 25